1. Field of the Invention
The present invention relates to a multichannel D/A converter including a plurality of D/A converters in a single chip.
2. Description of the Background Art
Recently, most electrical appliances such as TV, VTR and the like have been equipped with remote controllers. Various units in the electrical appliance are controlled by a microcomputer, based on a signal transmitted by the remote controller. Accordingly increased is the necessity of converting a digital signal which is the control signal of the microcomputer into an analog signal for practically controlling the various units in the electrical appliance. A large number of D/A converters have been required.
In a TV, for example, it is common that the microcomputer controls the volume, picture brightness, white balance and the like by means of the remote controller. For the control by the microcomputer, a single D/A converter is required for each of the units to be controlled. A multichannel D/A converter which includes a plurality of D/A converters integrated on a single semiconductor chip meets the aforesaid requirement.
FIG. 7 illustrates a conventional multichannel D/A converter. The multichannel D/A converter comprises 2.sup.n -number of (1-CH (channel) to 2.sup.n -CH) D/A converters 5. There are provided 2.sup.n -number of data latches 2 in correspondence to the D/A converters 5.
An (l+n)-bit shift register 1 serially receives an input data DI from an input terminal 22 in synchronism with a clock CLK inputted from a clock terminal 21, and stores a digital data having a total of (l+n) bits. The digital data includes D/A conversion data D.sub.OD to D.sub.(1-1)D (generically referred to as "DD" hereinafter) of 1 bit and addressing data D.sub.OA to D.sub.(n-1)A (generically referred to as "DS" hereinafter) of n bits.
The 2.sup.n -number of (1-CH to 2.sup.n -CH) data latches 2 each of which can store 1 bit are connected in parallel in correspondence to the D/A conversion data DD of the shift register 1.
The addressing data DS of the shift register 1 is inputted to an address decoder 3. The address decoder 3 decodes the addressing data DS and sets one of 2.sup.n -number of output lines to "H". The 2.sup.n -number of output lines are connected to the first input portions of 2.sup.n -number of AND gates 4, respectively. A data load signal LD from a data load terminal 23 is applied to the second input portions of the 2.sup.n -number of AND gates 4 in common. The outputs of the AND gates 4 are applied to the 1-CH to 2.sup.n -CH data latches 2 respectively.
Controlled by the respective outputs of the AND gates 4, the data latches 2 receive the D/A conversion data DD of the shift register 1 in parallel and output the D/A conversion data DD to the corresponding D/A converters 5.
FIG. 8 is a waveform chart showing the input timings of various signals in the multichannel D/A converter of FIG. 7.
In synchronism with the rising edge of the clock signal CLK, the input data DI is serially inputted to the shift register 1 in the form of the D/A conversion data DD or the addressing data DS. While the data load signal LD is at the "H" level, the D/A conversion data DD is latched by only the data latch 2 designated by the address decoder 3, that is, the data latch 2 connected to the output portion of the AND gate 4 having the first input portion associated with the output line at the "H" level of the address decoder 3.
Reference voltages V.sub.refU and V.sub.refL from reference voltage input terminals 24 and 25 are applied to the 1-CH to 2.sup.n -CH D/A converters 5 in common. The converters 5 perform D/A conversion on the D/A conversion data DD stored in the corresponding data latches 2 to output analog signals DA from corresponding data output terminals 26.
The conventional multichannel D/A converter formed on the single chip is structured as above mentioned. The D/A converters 5 of respective channels receive the reference voltages V.sub.refU and V.sub.refL from the reference voltage input terminals 24 and 25 in common. Hence, there has been a problem that dynamic ranges for the respective D/A converters 5 cannot be set individually.
For individually setting the dynamic ranges for the respective D/A converts 5, different reference voltages must be applied to the converters 5, so that it is necessary to provide the reference voltage input terminals for each of the D/A converters 5. A large number of external terminals are needed. This results in increased costs and a large packaging area for integration, as is not suitable for practical use.